Skip to content

Fix declassign regs #136

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
wants to merge 3 commits into
base: develop
Choose a base branch
from
Open

Fix declassign regs #136

wants to merge 3 commits into from

Conversation

Jiahui17
Copy link

@Jiahui17 Jiahui17 commented Mar 18, 2025 •
edited
Loading

Problem:

In Verilog, the statement

reg my_reg = 0;

is the same as

reg my_reg;
initial my_reg = 0;

whereas in the current HEAD, the statement above
is translated to

reg my_reg; assign my_reg = 0;

Solution

This commit fixes this bug by converting the assignment ast node to a blocking assignment wrapped in an initial block.

Jiahui17 added 3 commits March 19, 2025 00:14
@Jiahui17
git: ignore generated files when installed using --editable
ccc6a23
@Jiahui17
parser: fix declassign of regs
8e24d26 
in verilog, the statement

```
reg my_reg = 0;
```

is the same as

```
reg my_reg;
initial my_reg = 0;
```

whereas in the current HEAD, the statement above
is translated to
```
reg my_reg; assign my_reg = 0;
```

This commit fixes this bug
@Jiahui17
fix unclear comment
8a4c192
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@Jiahui17